Designing the Low - Power M • CORETM Architecture
نویسندگان
چکیده
The M•CORE microRISC architecture has been developed to address the growing need for long battery life among today’s portable applications. In this paper, we will present the low-power design techniques and architectural trade-offs made during the development of this processor. Specifically, we will discuss the initial benchmarking, the development of the Instruction Set Architecture (ISA), the custom datapath design, and the clocking methodology . Finally, we will discuss two system solutions utilizing the M•CORE processor, presenting power, area, and performance metrics. Jeff Scott, Lea Hwang Lee, John Arends, Bill Moyer M•CORE Technology Center Semiconductor Products Sector Motorola, Inc. TX77/F51, 7600-C Capital of Texas Highway, Austin, TX 78731 {jscott,leahwang,arends,billm}@lakewood.sps.mot.com Designing the Low-Power M•CORETM Architecture
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